Abstract
Two-dimensional (2D) semiconductors have shown great potential for monolithic three-dimensional (M3D) integration due to their dangling-bonds-free surface and the ability to integrate to various substrates without the conventional constraint of lattice matching1,2,3,4,5,6,7,8,9,10. However, with atomically thin body thickness, 2D semiconductors are not compatible with various high-energy processes in microelectronics11,12,13, where the M3D integration of multiple 2D circuit tiers is challenging. Here we report an alternative low-temperature M3D integration approach by van der Waals (vdW) lamination of entire prefabricated circuit tiers, where the processing temperature is controlled to 120 °C. By further repeating the vdW lamination process tier by tier, an M3D integrated system is achieved with 10 circuit tiers in the vertical direction, overcoming previous thermal budget limitations. Detailed electrical characterization demonstrates the bottom 2D transistor is not impacted after repetitively laminating vdW circuit tiers on top. Furthermore, by vertically connecting devices within different tiers through vdW inter-tier vias, various logic and heterogeneous structures are realized with desired system functions. Our demonstration provides a low-temperature route towards fabricating M3D circuits with increased numbers of tiers.
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Data availability
The data that support the findings of this study are available within the paper and the Extended Data. Other relevant data are available from the corresponding author on reasonable request. Source data are provided with this paper.
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Acknowledgements
Y. Liu acknowledges the financial support from the National Natural Science Foundation of China (Grant Nos. 51991341, 62325402, U22A2074 and 52221001), from the National Key R&D Program of China (Grant No. 2021YFA1200503) and from the Science and Technology Innovation Program of Hunan Province (Grant No. 2022RC3062). D.L. acknowledges the financial support from the National Natural Science Foundation of China (Grant No. 62304075), from the China Postdoctoral Science Foundation (Grant No. GZC20230754) and from the Hunan Provincial Natural Science Foundation of China (Grant No. 2023JJ40170). We acknowledge the Analytical Instrumentation Center of Hunan University for device characterization (Raman and focused ion beam).
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Y. Liu conceived the research and designed the experiments. D.L. led the device fabrication and electrical characterization. Y.C., L.M., Q.T., Z. Li, L.K., L. Liu, X.Y., S.D., X.L., Y. Li, Y.W., Y.H. and L. Liao contributed to device fabrication and electrical measurement. Z. Lu contributed to the fabrication of dielectric. R.W. and X.D. contributed to the CVD MoS2. Y. Liu and D.L. co-wrote the paper. All authors discussed the results and commented on the manuscript.
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Extended data figures and tables
Extended Data Fig. 1 Schematics of circuit tier pre-fabrication on a sacrificial substrate.
a, Deposition of source-drain electrodes and interconnects through thermal deposition. b, Spin-coating low-κ ITD. c, Dry-etching inter-tier holes of ITD. d, Deposition of ITV connections of ITD. e, Deposition of gate electrode and interconnects. f, ALD deposition of high-κ gate dielectric. g, Wet-etching inter-tier holes of Al2O3. h, Creation of ITV connections of Al2O3.
Extended Data Fig. 2 Optical images of the wafer-scale integration processes by one-step vdW circuit tier.
a-c, Photos of 2-inch circuit tier pre-fabricated on sacrificial wafer (a), physically released on PDMS (b) and laminated on target 2D substrate (c). d-f, Corresponding optical images of panel a-c.
Extended Data Fig. 3 Alignment process of vdW M3D integration.
a, b, Schematical illustration of the alignment system using x-y-z manipulator. c, Schematic (upper part) and corresponding optical image (lower part) of the left alignment markers with well-fitted position. d, Optical image of the aligned structure between top circuit tier with bottom MoS2 layer using four alignment markers. e, Schematic (upper part) and corresponding optical image (lower part) of the right alignment markers with well-fitted position. Slight mis-placement are intentionally introduced in the makers in panel c, e for better observation.
Extended Data Fig. 4 10 MoS2 circuit tiers vdW M3D integration.
Optical images during the tier-by-tier lamination processes of 10 MoS2 circuit tiers M3D integration. The monolayer MoS2 arrays are prepared by using CVD.
Extended Data Fig. 5 Cross-sectional scanning electron microscope characterization.
a, Cross-sectional scanning electron microscope image of 10 MoS2 circuit tiers M3D integration. b, c, Cross-sectional scanning electron microscope image of MoS2 transistors within tier #8 and #9 (b), and its corresponding device schematic (c). Note it is still challenging to fabricate sample for cross-sectional characterization, because the CPVA ITD layer could be molten during the high-energy FIB (focused ion beam) cutting process, leading to tier delamination, bending of Au ITV layer, or even total sample failure.
Extended Data Fig. 6 Characterization of ITD layer.
a, b, Optical images of laminated 700 nm SiO2 layer as ITD, where clear wrinkles, bubbles (a), and cracks (b) are observed due to the brittle nature of oxide film. c, Capacitance-voltage characteristic of 700 nm CPVA at 100 kHz measurement frequency. Inset is the schematics of metal-insulator-metal device structure for capacitance measurement.
Extended Data Fig. 7 Extraction of contact resistance.
a, Transfer curves of monolayer MoS2 transistor fabricated by one-step vdW integration with different channel lengths. b, Extracted contact resistance through transfer length method.
Extended Data Fig. 8 The electrical properties of MoS2 transistors distributed in 10 tiers.
a, Schematic diagram of 10-tiers M3D system. b, c, Transfer curves of monolayer MoS2 transistors within each tier (from tier #1 to tier #10). 10 transistors are measured in each tier, and the bias voltage is fixed at 1 V. d, e, Summary of the mobility (d) and on-state current (e) of each tier MoS2 transistors. The devices (distributed within 10 different tiers) exhibit consistent electron mobility and on-state current, indicating the vdW integration of upper tiers won’t impact the device performance of lower tiers. The error bars are determined from the statistical standard deviations of 10 devices for each tier.
Extended Data Fig. 9 Output curves under different fabrication processes.
a-d, Output curves of MoS2 transistors with vdW (a), evaporation (b), coating (c) and etching (d) fabrication processes. e, Output curves of another MoS2 transistor with higher Vds (30 V) using vdW lamination process, exhibiting saturation behaviour, indicating the vdW integrated devices are functioning adequately and the device properties could be well-retained. The gate voltages are from −20 V to 60 V with 20 V step.
Extended Data Fig. 10 Raman spectra of monolayer MoS2 under different fabrication processes.
a, Raman spectra of initial MoS2, after vdW laminated CPVA, after spin-coated CPVA, and after plasma etching (MoS2 with CPVA protection) at 150 W for 20 min. b, c, \({{\rm{E}}}_{2{\rm{g}}}^{1}\) and A1g Raman position (b) and full width at half maxima (c) of monolayer MoS2 under different fabrication processes. After laminating interlayer dielectric CPVA, the \({{\rm{E}}}_{2{\rm{g}}}^{1}\) Raman position and its peak FWHM remain unchanged, suggesting the minimized defects or strain during the lamination process. In contrast, by directly spin-coating CPVA on top of MoS2 surface, \({{\rm{E}}}_{2{\rm{g}}}^{1}\) peak blue-shifts by 0.9 cm−1 and its FWHM increases by 0.6 cm−1, indicating the generation of additional defects or strains during the solution-based coating processes. Similarly, the \({{\rm{E}}}_{2{\rm{g}}}^{1}\) peak exhibits large shifts of 2.0 cm−1 with FWHM increases of 1.2 cm−1 after plasma process, indicating the MoS2 delicate lattice could still be impacted by the plasma process, even covered by 700 nm thick CPAV layer.
Extended Data Fig. 11 Statistics of electrical properties of MoS2 devices through both vdW process and conventional high-energy process.
a, Transfer curves of 200 monolayer MoS2 transistors (located on the bottom tier) fabricated by both vdW process and high-energy process (including S/D, ITD, ITV and measurement pad; 100 transistors for each type). b, c, Summary of the carrier mobility (b) and on-state current (c) of both processes, where the vdW devices exhibits higher device performance and better uniformity.
Extended Data Fig. 12 vdW integration of MoS2 devices on thermal expandable PDMS substrate.
a, b, Optical images of MoS2 flake on PDMS substrate before (a) and after (b) heating at 150 °C, exhibiting clear crack and wrinkle due to the substrate thermal expanding. c, d, Output curves (c) and transfer curves (d) of monolayer top-gate MoS2 transistor on PDMS substrate by vdW integrating circuit tier. e, Voltage transfer characteristics and corresponding voltage gains (inset) of inverter on PDMS substrate with different Vdd from 1 to 5 V. MoS2 flakes are exfoliated for proof-of concept demonstration.
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Lu, D., Chen, Y., Lu, Z. et al. Monolithic three-dimensional tier-by-tier integration via van der Waals lamination. Nature 630, 340–345 (2024). https://doi.org/10.1038/s41586-024-07406-z
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DOI: https://doi.org/10.1038/s41586-024-07406-z
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