Extended Data Fig. 3: Alignment process of vdW M3D integration.

a, b, Schematical illustration of the alignment system using x-y-z manipulator. c, Schematic (upper part) and corresponding optical image (lower part) of the left alignment markers with well-fitted position. d, Optical image of the aligned structure between top circuit tier with bottom MoS₂ layer using four alignment markers. e, Schematic (upper part) and corresponding optical image (lower part) of the right alignment markers with well-fitted position. Slight mis-placement are intentionally introduced in the makers in panel c, e for better observation.