Extended Data Fig. 1: Schematics of circuit tier pre-fabrication on a sacrificial substrate. | Nature

Extended Data Fig. 1: Schematics of circuit tier pre-fabrication on a sacrificial substrate.

From: Monolithic three-dimensional tier-by-tier integration via van der Waals lamination

Extended Data Fig. 1

a, Deposition of source-drain electrodes and interconnects through thermal deposition. b, Spin-coating low-κ ITD. c, Dry-etching inter-tier holes of ITD. d, Deposition of ITV connections of ITD. e, Deposition of gate electrode and interconnects. f, ALD deposition of high-κ gate dielectric. g, Wet-etching inter-tier holes of Al2O3. h, Creation of ITV connections of Al2O3.

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