Extended Data Fig. 1: Schematics of circuit tier pre-fabrication on a sacrificial substrate.
From: Monolithic three-dimensional tier-by-tier integration via van der Waals lamination
![Extended Data Fig. 1](https://cdn.statically.io/img/media.springernature.com/full/springer-static/esm/art%3A10.1038%2Fs41586-024-07406-z/MediaObjects/41586_2024_7406_Fig5_ESM.jpg)
a, Deposition of source-drain electrodes and interconnects through thermal deposition. b, Spin-coating low-κ ITD. c, Dry-etching inter-tier holes of ITD. d, Deposition of ITV connections of ITD. e, Deposition of gate electrode and interconnects. f, ALD deposition of high-κ gate dielectric. g, Wet-etching inter-tier holes of Al2O3. h, Creation of ITV connections of Al2O3.