Extended Data Fig. 12: vdW integration of MoS2 devices on thermal expandable PDMS substrate.
From: Monolithic three-dimensional tier-by-tier integration via van der Waals lamination
a, b, Optical images of MoS2 flake on PDMS substrate before (a) and after (b) heating at 150 °C, exhibiting clear crack and wrinkle due to the substrate thermal expanding. c, d, Output curves (c) and transfer curves (d) of monolayer top-gate MoS2 transistor on PDMS substrate by vdW integrating circuit tier. e, Voltage transfer characteristics and corresponding voltage gains (inset) of inverter on PDMS substrate with different Vdd from 1 to 5 V. MoS2 flakes are exfoliated for proof-of concept demonstration.