Extended Data Fig. 2: Optical images of the wafer-scale integration processes by one-step vdW circuit tier.
From: Monolithic three-dimensional tier-by-tier integration via van der Waals lamination
a-c, Photos of 2-inch circuit tier pre-fabricated on sacrificial wafer (a), physically released on PDMS (b) and laminated on target 2D substrate (c). d-f, Corresponding optical images of panel a-c.