Extended Data Fig. 5: Cross-sectional scanning electron microscope characterization.
From: Monolithic three-dimensional tier-by-tier integration via van der Waals lamination
a, Cross-sectional scanning electron microscope image of 10 MoS2 circuit tiers M3D integration. b, c, Cross-sectional scanning electron microscope image of MoS2 transistors within tier #8 and #9 (b), and its corresponding device schematic (c). Note it is still challenging to fabricate sample for cross-sectional characterization, because the CPVA ITD layer could be molten during the high-energy FIB (focused ion beam) cutting process, leading to tier delamination, bending of Au ITV layer, or even total sample failure.