Extended Data Fig. 11: Statistics of electrical properties of MoS2 devices through both vdW process and conventional high-energy process.
From: Monolithic three-dimensional tier-by-tier integration via van der Waals lamination
a, Transfer curves of 200 monolayer MoS2 transistors (located on the bottom tier) fabricated by both vdW process and high-energy process (including S/D, ITD, ITV and measurement pad; 100 transistors for each type). b, c, Summary of the carrier mobility (b) and on-state current (c) of both processes, where the vdW devices exhibits higher device performance and better uniformity.