Engineering MoSe₂/MoS₂ heterojunction traps in 2D transistors for multilevel memory, multiscale display, and synaptic functions

In the fourth industrial revolution, which is deeply related to big data, the internet of things (IoT), and artificial intelligence (AI)^1,2, Si-based device technology has faced imminent challenges for massive data processing and storage because of its own limit in device integration density. To cope with the limit, multivalue logic, multilevel memory, and synaptic memory appear promising ways to secure more efficient data processing and memory capacity. For instance, oxide-based resistive random access memory (RRAM) of two-terminal structures has been studied to achieve such purposes, particularly for synaptic/neuromorphic memory functions^3,4,5. Still, it is under development for practical application due to random stochastic filament formation and cross-talk issues. To circumvent the issues of RRAM, three-terminal memories have also been suggested for practical circuit applications^6,7,8. Intriguingly, such three-terminal neuromorphic devices can be realized with two-dimensional (2D) transition metal dichalcogenides (TMDs), which have attracted much attention due to their unique physical properties^9,10,11,12. In fact, there have been quite a few studies for bistable (two level: Program and Erase) memory transistors composed of diverse 2D van der Waals (vdW) materials: TMDs, graphene, and h-BN, among others^{13,14,15,16,17}. However, multilevel memories in 2D TMD channel-based field-effect transistor (FET) structures are only a few in report and also mostly require high operating voltages and long pulse widths^{18,19,20,21,22}. (See Supplementary Table 1).

In the present study, we have fabricated multilevel long-term memory devices practically operating with 60 μs-short pulses at low 7 V based on vdW heterostack (HS) n-TMD FETs, which were extended to multiscale display and neuromorphic memory applications. In principle, all kinds of semiconducting TMDs can be utilized for vdW HS FETs including p-type TMDs. Here, 2D n-MoSe₂/n-MoS₂ structure was used as a channel of HS FET. Our HS channel FETs initially operate as a simple bistable nonvolatile memory FET with Program and Erase states (PR/ER current ratio ~10⁵), which are defined under positive and negative gate voltage (V_GS) pulses, respectively. The HS memory device properly exploits the V_GS-induced trapping/de-trapping phenomena for such Program/Erase functioning, as the trap density-of-state (DOS) of electrons exists at the interface between 2D-like thin MoS₂ and MoSe₂. Interestingly, the stacking sequence between MoS₂ and MoSe₂ is found to be important for memory retention performance, which needs a proper heterojunction barrier. Therefore, n-MoS₂ in contact with a dielectric serves as the main channel layer for electron conduction in FET, and n-MoSe₂ then contacts the source/drain (S/D) electrode. More usefully, trapped electron density could be modulated by the amount of pulsed V_GS, enabling the HS device to achieve multilevel long-term memory or multivalue data storage. For the multilevel memory functions, our device could distinctively demonstrate at least seven-level states of drain current (I_D) by varying V_GS. The multilevel memory device also nicely went through a cyclic endurance test that enforced >100 pulse cycles; a cycle includes 7 V_GS pulses to match seven I_D levels. The seven different levels of I_D were further visualized with multiscale light emissions when our memory FET was integrated into a green organic light-emitting diode (OLED) pixel circuit, which then appears analogous to a conventional gray-scale active matrix pixel circuit composed of two FETs and one OLED. As a final interest, our device was put to neuromorphic operation for synaptic devices in an artificial neural network (ANN), where long-term multilevel memories are necessary. Based on potentiation-depression (P-D) characteristics of our device under multiple 60-µs-short V_GS pulses, the simulation results show ~94% recognition accuracy. We regard our unique HS channel FET to be an interesting and promising electron device undertaking multifunctional operations related to the upcoming fourth industrial revolution era.

Materials and device characterization of stacked channel memory FET

Figure 1a illustrates a 3D schematic structure of a MoSe₂/MoS₂ stacked channel FET with polystyrene (PS)-brush-coated Al₂O₃ gate insulator and Au gate (G) electrode that is patterned on a glass substrate. High-k Al₂O₃ is chosen for gate insulator, preferred to conventional SiO₂, in consideration of low voltage operation of our nonvolatile HS multilevel memory FET. To form the 2D vdW heterojunction stack channel, a MoS₂ flake is first transferred on a PS-brush/Al₂O₃ gate insulator in sequence. The MoSe₂ flake is then stacked on the MoS₂, covering the whole area of the bottom MoS₂ so that the Au S/D electrode may contact the top surface of MoSe₂. An ultrathin PS-brush was used to make the surface of the gate oxide more hydrophobic, which would significantly reduce the trap densities at the channel/gate insulator interface^23,24. Particularly, because atomically thin 2D TMD channels are vulnerable to interface traps, such PS-brush treatment is regarded as very important in the present study. As a result, trapped electron charges are mainly located at MoSe₂/MoS₂ interface, not at the channel/dielectric interface. The device fabrication details, including PS-brush formation, are later described in the Methods part. The optical microscopy (OM) image of our fabricated FET device is shown in Fig. 1b. A cross-sectional scanning transmission electron microscopy (STEM) image is observed in low magnification in Fig. 1c, showing the whole structure of the MoSe₂-MoS₂ stack/2 nm PS-brush/30 nm Al₂O₃/Au-Ti gate on the glass substrate. A STEM image of the MoSe₂-MoS₂ stack at higher magnification is shown in Fig. 1d, along with energy-dispersive X-ray spectroscopy (EDS) mapping for chemical elements, which could distinguish Se- and S-included layers. The high-resolution STEM image shows that the interface between MoS₂ and the MoSe₂ flake is well-formed, and their thicknesses appear to be ~1.95 nm (3 L) and 3.83 nm (6 L), respectively^25,26. More details for EDS analysis are found in Supplementary Fig. 1. Raman spectra in Fig. 1e also evidence the physicochemical identities of MoS₂, MoSe₂, and the MoSe₂/MoS₂ stack, showing that the local vibrational peaks in the stack are accurately matched to those of a single flake. The electrical properties and transfer characteristics (drain current versus gate-source voltage: I_D–V_GS) of our stack channel FET is shown in Fig. 1f. Our FET exhibits a high ON/OFF I_D ratio of ~10⁵ and ON I_D of a hundred nA at the drain-source voltage, V_DS = 0.1 V. Clockwise hysteresis appears when a double (±) V_GS sweep was conducted from −7 to 7 V. (The hysteresis window of our device gradually increased by increasing the V_GS sweep. See Supplementary Fig. 2 for further details of this device.) Short Program (7 V, 60 μs)/Erase (−7 V, 60 μs) pulse experiments were also conducted on our device. (See Supplementary Fig. 2 for all other results from 60 μs, 1 ms, 10 ms, 100 ms, 500 ms, and 1 s pulses. No significant difference in ON/OFF I_D ratio was observed between 60 μs and 1 s pulses.) After the pulse, our device displays a dramatic change in the channel conductivity, showing two distinct states in Fig. 1f (Program/Erase I_D ratio of ~10⁵, note violet vs. black square). Figure 1g displays the cyclic endurance results of our HS memory FET, which were measured during 400 repeated Program/Erase pulse operations. The Program/Erase I_D ratio appears well-endured at ~10³. The memory retention properties of our device were also measured, as shown in Fig. 1h, where a high Program/Erase I_D ratio of ~10³ is still observed at V_DS = 0.1 V (and V_GS = −1 V), even after 10⁴ s elapses since the time of Erase (−7 V, 60 μs) and Program (+7 V, 60 μs) pulses. When the pulse width increases to 1 s, Program/Erase ratio in retention increases to 10⁴. Consequently, it was confirmed that the stacking channel FET could work as a simple nonvolatile memory device to distinguish two-level data storage at least. On the one hand, the other FET fabricated with a reversed stacking sequence of MoS₂/MoSe₂ showed much inferior retention of a small Program/Erase I_D ratio of ~40 only after 500 s. We attribute this inferior retention behavior to the possibility that the offset-induced barrier at the initial MoSe₂/MoS₂ heterojunction vanishes at the reversed MoS₂/MoSe₂ stack junction. In this case, Erase pulse is well functioning to keep its state, but Program state may not be well maintained after pulse owing to some charge leakage to the S/D electrode. The offset barrier effects are well described in the band diagrams of Supplementary Fig. 3. Hence, it is important for nonvolatile memory performance whether the offset-induced barrier exists or not. Such charge leakage results in the rapid increase of Program I_D (see Supplementary Fig. 3d).

a 3D schematic structure and b optical microscopy image of a MoSe₂/MoS₂ stacked channel FET. Scale bar, 10 μm. c Cross-sectional STEM image for whole layer structure of MoSe₂-MoS₂ stack/2 nm PS-brush/30 nm Al₂O₃/Au-Ti gate on a glass substrate in low magnification. Scale bar, 10 nm. d High-resolution STEM image (left) and EDS mapping (right) of the MoSe₂-MoS₂ stack. Scale bar, 1 nm. e Raman spectra for the chemical/physical identities of MoS₂, MoSe₂, and MoSe₂/MoS₂ stack. f Transfer characteristics of the MoSe₂/MoS₂ stacked channel FET at V_DS = 0.1 V. Short program (7 V, 60 μs)/Erase (−7 V, 60 μs) pulse experiments are also conducted on the device, showing two distinct states (Program/Erase I_D ratio of ~10⁵, note violet vs. the black line). g Cyclic endurance results of the heterostack memory FET, which are measured during 400 times of repeated Program/Erase pulse operations. h Memory retention properties of the heterostack memory FET. High Program/Erase I_D ratio of ~1000 is observed at V_DS = 0.1 V even after 10,000 s elapse since Erase (−7 V, 60 μs) and Program (+7 V, 60 μs) pulses.

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Operation mechanism of stacked channel memory device

As for the aforementioned memory functions, we suspect any contribution of possible charge traps at the MoSe₂/MoS₂ heterojunction interface as the origin of such nonvolatile function, although no conspicuous defect signs were observed from the high-resolution STEM image of the interface (Fig. 1d). This is because single-MoS₂-channel FET with the same oxide dielectric (PS-brush/Al₂O₃) hardly shows a large hysteresis, unlike the case of an HS channel FET. When we fabricated a MoS₂ single-channel FET with a PS-brush layer, its transfer curve showed only a little hysteresis (~0.2 V), as seen in Supplementary Fig. 4. Thus, more information was needed on the possible origin of the memory function in the present FET device. Figure 2a shows an OM image of another MoSe₂/MoS₂ stack channel memory FET along with scanning Kelvin probe microscopy (SKPM) mapping for both stacked and single-channel areas. The work function of MoSe₂ alone appeared to be 4.52 eV while that of the same MoSe₂ but stacked on MoS₂ was slightly smaller to be 4.49 eV, which means that n-MoSe₂ in the stack area is influenced by n-MoS₂. This is particularly due to electron charge transfer taking place from MoS₂ to MoSe₂ because of a Fermi level (E_F) difference between the two n-type TMDs. Such extra electron charges would increase E_F as transferred to n-MoSe₂ and some charges should be trapped near or at the MoSe₂/MoS₂ interface. Based on our SKPM results and the reported band diagram of individual MoS₂ and MoSe₂^27,28,29, a band diagram of the MoSe₂/MoS₂ heterojunction could be constructed as seen in Fig. 2b. The interfacial electron trap DOS might come from a mechanical exfoliation and dry-transfer process of 2D TMD flakes³⁰ while the nature of deep level point defects inside MoS₂ is also known as related to sulfur vacancies³¹. Fig. 2c–e and Fig. 2f–h illustrate 2D schematic structures and corresponding band diagrams of our MoSe₂/MoS₂ stack channel FET, respectively. At the pristine states in Fig. 2c, f, some of the trap DOS is initially occupied by electrons. Under Program pulse (V_GS = 7 V, 60 μs), interface traps and DOS are completely filled with electrons drawn from the S/D electrode, as shown in Fig. 2d, g. Even after the pulse, the filled DOS was effectively maintained without losing many electrons because of the heterojunction energy barrier, as seen in Fig. 2f. As a result, electron accumulation near the MoS₂ channel/dielectric interface becomes electrostatically uneasy due to the trapped electrons. The higher gate voltage is thus required for the electron accumulation at the MoS₂/dielectric interface, when compared with that of pristine state. Hence, the threshold voltage (V_TH) of the stack channel memory FET shifts toward a positive bias direction. Under Erase pulse (V_GS = −7 V, 60 μs), electrons in the trap sites will become de-trapped as shown in Fig. 2e, h. After the de-trapping of electrons, there is no electrostatic hindrance for electron accumulation; the MoS₂ bottom channel of our memory FET is easily controlled by the bottom gate without the trap-induced electrostatic hindrance. V_TH now shifts toward more negative than that of the pristine state. Consequently, channel conductance of the memory FET can be modulated between low conductance (Program) and high conductance states (Erase) by a V_GS pulse.

a OM image of a MoSe₂/MoS₂ stack channel memory FET, along with its scanning kelvin probe microscopy mapping near the center of the stacked channel area. Scale bars, 10 μm (left) and 1 μm (right). b Band diagram of MoSe₂/MoS₂ heterojunction. c–e 2D schematic structures of our MoSe₂/MoS₂ stack channel FET to describe electron traps at the MoSe₂/MoS₂ heterojunction interface as the origin of such nonvolatile function. The electron trap site is partially filled, fully filled, and completely evacuated under 0, +7 V, and −7 V gate pulses, respectively. f–h Analytical energy band diagrams of MoSe₂/MoS₂ heterojunction stack channel FET under corresponding gate voltage conditions in c–e device figures.

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Device performance of MoSe₂/MoS₂ stack channel multilevel memory FET

More interesting phenomena than the two-state (PR/ER) memory effects would be the multistep modulation of channel conductance, which is obtained by filling or evacuating the trap DOS gradually. Figure 3a shows the transfer curves as measured under a double sweep of V_GS in many steps (seven steps of V_GS from ±1 V to ±7 V), where V_TH values are defined as V_GS at 1 nA of I_D. Relations between the V_TH and V_GS sweep range are plotted in Fig. 3b, wherein the V_TH values in all the transfer curve hysteresis appear a little asymmetric but show their initial value fixed at −1.5 V (as indicated by the dark dashed line). Such asymmetry probably results from the fact that the low-energy part of the whole trap DOS area was initially occupied by electrons even before applying V_GS or pulses, and the occupied DOS area was larger than the unoccupied area. Hence, a highly negative V_GS (more negative than −5 V) may completely evacuate the trapped electrons from the DOS site (black line) while a relatively small positive V_GS (larger than +1.0 V) attracts the electrons to fill the trap DOS (red line). It is worth noting the inset band diagram, where the initially filled (pristine)-DOS state is indicated by a red line. Our understanding from Fig. 3a, b is that V_TH changes gradually under incremental V_GS steps, which may indicate that charge trapping/de-trapping could also be incrementally controllable by the magnitude of the V_GS pulse. In fact, such incremental V_TH change by a short V_GS pulse (60 μs to 1 s width) correspondingly comes along with an I_D change in light of transfer characteristics. Figure 3c directly shows the I_D modulation by the magnitude of 60 μs-short V_GS pulse in our HS memory FET as measured at V_GS of –0.5 V at V_DS = 0.1 V for I_D recording. Many I_D states are achievable by applying a V_GS pulse, and here seven states are demonstrated for example ID7, ID6, ID5, ID4, ID3, ID2, and ID1 for −7, 2, 3, 4, 5, 6, and 7 V pulses, respectively. Starting from ~30 nA of the ID7 state, I_D decreased to ~200 fA of ID1 with a pulse voltage change in the above order. Cyclic endurance measurement in Fig. 3d exhibits the same discrete ID7, ID6, ID5, ID4, ID3, ID2, and ID1 states without much variation for 100 cycles, as shown in Fig. 3c. Among the 100 cycles, we zoom into a few cycles to see their details in Fig. 3e, where under cyclic V_GS pulses all seven I_D states are clearly repeated in order. Even if random arbitrary V_GS pulses are also applied, as shown in the upper plots of Fig. 3f, all seven I_D states keep their own original levels according to the random order (although two states are skipped here for properly visible demonstration). Moreover, in the case of Fig. 3f, long-term multilevel over 70 s appears to be kept or remembered for each state after a 60 μs V_GS pulse, showing that our HS FET plays very well as a multilevel memory device.

a Transfer curves of MoSe₂/MoS₂ stack channel memory FET, showing asymmetric memory hysteresis behavior as measured under the double sweep of V_GS. b Plots showing the relations between V_TH and V_GS sweep range. Initial V_TH is indicated by a dark dashed line ~−1.5 V. c I_D modulation by the amount of V_GS pulse in the heterostack memory FET as measured in a V_GS range (−0.51 V ~−0.49 V) at V_DS = 0.1 V. Arbitrarily taken, seven states are demonstrated: ID7, ID6, ID5, ID4, ID3, ID2, and ID1 for −7, 2, 3, 4, 5, 6, and 7 V pulses. d Cyclic endurance results of the heterostack multilevel memory FET for 100 cycles. e A few cycles of the endurance test to see details, where under cyclic V_GS pulses all the seven I_D states are clearly repeated in order. (Each cycle takes 5 s and each V_GS pulse does <1 s). f Long-term memory retention over 70 s for each state after 60 μs V_GS pulse. All five I_D states keep their own original levels according to the random order.

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Multilevel light-emitting of OLED pixel with stack channel memory FET

The above-mentioned long-term multilevel memory functions could be more visibly demonstrated with a practical application such as gray or multiscale OLED pixel switching, for which our MoSe₂/MoS₂ stack channel FET is integrated into an OLED circuit. Figure 4a shows an OM image of the HS memory FET used for this demonstration, and its transfer curves are displayed in Fig. 4b (more details for the device are found along with output characteristics in Supplementary Fig. 5). Figure 4b also presents the OLED pixel circuit in the inset, where a green OLED device is connected in series. Under a supplied voltage (V_DD) and 1 s V_GS pulse, OLED current (I_OLED) was controlled. Figure 4c shows the retention properties of I_OLED after V_GS pulses for the OLED ON and OFF states. An ON/OFF I_OLED ratio of ~200 seems to be maintained for longer than 1500 s without much variation in OLED brightness. Inset OLED pixel images at different retentions of 500 s, 1000 s, and 1500 s show almost identical brightness. Figure 4b displays seven levels (states) of I_D under seven different V_GS pulses in the memory FET; these could become seven states of I_OLED under seven input (V_IN) pulses via integration into the OLED pixel circuit. Figure 4d shows multiscale pixel illumination that appears clear with five brightness levels according to each corresponding I_OLED and V_OUT value although the last three states (ID3, ID2, and ID1) merged into the same dark (OFF) state. [For better understanding, please see the I–V curve of the green OLED in Supplementary Fig. 6, where the OLED turns on at 2 V and an I_OLED of a few nA is already too low to emit lights (or barely emitting dim lights)]. Despite two missing I_OLED states, every other state lasts stably for longer than ~500 s; we prepared a short video (multiscale OLED with HS FET.mp4) in Supplementary Information for a more visible demonstration of gray-scale multilevel pixel operation.

a OM image of another heterostack memory FET used for a green OLED pixel demonstration. Scale bar, 10 μm. b I_D modulation in the heterostack multilevel memory FET as measured at V_GS of 0 V and V_DS = 2 V, displaying seven levels (states) of I_D under seven different V_GS pulses, and inset is an OLED pixel circuit, where a green OLED device is connected in series. c Retention properties of I_OLED after V_GS pulses for OLED On and OFF states. An ON/OFF I_OLED ratio of ~200 seems maintained for longer than 1500 s. Inset OLED pixel images at different retentions of 500 s, 1000 s, and 1500 s, show almost the same brightness. d Time-domain I_OLED plot and corresponding V_OUT – time plot, as obtained under different pulses. Gray-scale pixel illumination appears clearly with five brightness levels as shown in the inset green OLED images.

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Synaptic memory behavior of stack channel FET

Apart from the V_GS-modulated multilevel memory functions, we have also attempted to mimic the biological synapse using our MoSe₂/MoS₂ stacked channel FET as inspired by cyclic memory endurance experiments. In the biological nervous system^32,33, the neurons are connected to each other through the synapse, which conveys electrical or chemical signals from pre-neuron to post-neuron. And the connectivity between neurons, named synaptic weight, can be modulated by the number of released neurotransmitters as shown in Fig. 5a. In our stack (or synaptic stack) channel FET of Fig. 5a, constant V_GS in pulse series serves as a presynaptic voltage (V_Pre) spike, which leads to a change of synaptic weight. A pulse (spike) number-modulated channel conductance, G (defined as I_D divided by V_DS = 0.1 V) is matched with synaptic weight, where I_D is analogous to postsynaptic current (I_Post). We applied 100 excitatory pulses for potentiation (negative V_Pre) and another 100 inhibitory pulses for depression (positive V_Pre) in series, as depicted in Fig. 5b. Figure 5c shows the monitored P-D plots depending on the diverse amplitude of excitatory pulse (−3.6 V, −3.7 V, −4 V, and −4.3 V with 60 μs width) and fixed inhibitory pulse amplitude of 3.7 V with 60 μs width; we only vary the amplitude of an excitatory pulse to analyze the variation behavior of maximum/minimum channel conductance ratio (G_Max/G_Min). Here, G_Max appears to become large by increasing the amplitude of pulses; a larger magnitude of V_Pre pulse evacuates more trapped electrons from the MoSe₂/MoS₂ interfacial trap DOS, resulting in larger channel conductance of synaptic device. Figure 5d shows two P-D pulse combinations (=−4.3 V/3.7 V and −3.7 V/3.7 V). In fact, a high G_Max/G_Min is no more important, once the ratio attains a certain high value (over ~40)³². The linearity of P-D plots becomes rather important in this case³⁴. According to the P-D plots of Fig. 5d, the potentiation linearity of the low G_Max/G_Min ratio case is apparently better than that of the high ratio plot. On the one hand, depression plots of both cases appear much deviated from ideal linearity. The very different linearity and asymmetry between potentiation and depression plot are intrinsically attributed to the band offset in MoSe₂/MoS₂ heterojunction band diagram, as shown in Fig. 2b. Owing to the shape of band offset at the heterojunction, electron trapping (for depression) is much easier than de-trapping (potentiation). That is why the linearity of potentiation is better than that of depression, which also causes asymmetric P-D curves. More details about the dependency of linearity on pulse amplitude are included in Supplementary Fig. 7 and Supplementary Table 2. We eventually perform ANN simulation for three cases: assuming perfect linearity and using actual data in any P-D plots of Fig. 5c, d. Figure 5e shows the schematics of multilayer perceptron (MLP) neural network constructed for classification of MNIST handwritten digits^33,35. It has three layers of neurons, and those layers are composed of 784 input neurons, 100 hidden neurons, and 10 output neurons, respectively³⁶. Three neuronal layers are connected by modeled synapse on the basis of the P-D plot of our stack channel memory. The modeled synapse is composed of our stack channel FET and switching transistor as shown in a circuit diagram of our ANN (Fig. 5f)^17,32. For Program (Erase) process, positive (negative) voltage is applied at the gate of the synaptic transistor, when the switching transistor is on. To read modulated conductivity of synaptic transistor channel, V_DS is applied, when the switching transistor is off. By utilizing the stochastic gradient descent (SGD) algorithm, we trained our ANN with 8000 images of the training subset selected at random from 60,000 images of the original training set. We then calculated a recognition accuracy as achieved from testing the trained ANN with 10,000 images of a testing set, which is totally separated data set from the training set. The simulation resulted in ~94% high accuracy on average whether G_Max/G_Min ratio is 115 or 61.7 when assuming perfect linearity in P-D plots, as shown in Fig. 5g which includes actual linearity-based simulation result. Of course, the accuracy from actual data-based ANN simulations appears limited to maximum ~77%, which could be, however, improved over 90% by way of proper circuitry designs. These results again indicate that the G_Max/G_Min ratio does not have to be high over a few tens in P-D plots, suggesting that a linear-shape plot is rather more important when G_Max/G_Min ratio is properly satisfied.

a Schematic illustration of a biological synapse in neuron system and our synaptic stack channel FET for neuromorphic function. b Illustration of a V_Pre pulse train composed of 100 excitatory pulses for potentiation and 100 inhibitory pulses for depression in sequence. c Monitored P-D plots depending on the diverse amplitude of excitatory pulse (−3.6 V, −3.7 V, −4 V, and −4.3 V with 60 μs width) and fixed inhibitory pulse (3.7 V with 60 μs width). d Two P-D conductance plots with G_Max/G_Min values of 115.2 and 61.7 as, respectively, obtained from the excitatory/inhibitory pulse combinations. The potentiation linearity of the low G_Max/G_Min ratio case is apparently better than that of the high ratio case. e Schematics of multilayer perceptron (MLP) neural network for classification of MNIST handwritten digits. f Circuit diagram of our artificial neural network (ANN) composed of modeled synapse and peripheral circuits, to perform program and read processes. The synapse consists of our stack channel FET and a switching transistor. g Simulation results exhibiting that the ANN using our stack channel FET demonstrates ~94% accuracy on average by assuming perfect linearity but only ~77% accuracy from actual P-D behavior whether G_Max/G_Min ratio is 115 or 61.7.

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In summary, we have studied multilevel memory devices operating under short pulse low voltage conditions (60 μs shortest, 7 V maximum), based on a vdW heterostacked n-MoSe₂/n-MoS₂ channel FET. Our HS channel FET initially appeared to operate as a simple bistable nonvolatile memory FET with Program and Erase states. The HS memory device properly exploited the V_GS-induced trapping/de-trapping phenomena for such Program/Erase functioning, which was nicely maintained for 10⁴ s-long retention times due to the existence of a heterojunction energy barrier between MoS₂ and MoSe₂. More interestingly, trapped electron density could be incrementally modulated by the magnitude of pulsed V_GS, enabling the HS device to achieve multilevel long-term memory. For a practical multiscale display demonstration, five different levels of I_D were visualized with modulated light emissions when our memory FET was integrated into a green OLED pixel circuit. In addition, our device was applied to a synaptic memory function. Based on the P-D characteristics of our device under multiple 60-µs-short V_GS pulses, the simulation resulted in an average ~94% recognition accuracy. We conclude that our HS channel FETs are interesting and promising enough to cope with future demanding multilevel memory electronics for the fourth industrial revolution.

Device fabrication

Glass substrates (Eagle 2000) were cleaned by sonication for 30 min in acetone and ethyl alcohol, respectively. As a bottom gate electrode, Au/Ti (10/5 nm) was patterned by photolithography, DC sputter-deposition, and the lift-off process. A 30-nm-thick Al₂O₃ was deposited by atomic layer deposition at 110 °C as a gate dielectric insulator. For the ultrathin PS-brush layer on Al₂O₃, dimethyl-chlorosilane-terminated PS (Polymer Source, Product No. P3881-SSiCl) was dissolved in toluene (Aldrich) solvent at a 10 mg/mL ratio. Before the PS-brush coating, oxygen plasma was conducted on the Al₂O₃ surface to make enough hydroxyl groups. PS solution was spin-coated and then the substrate was put in the oven to be annealed at 170 °C for 48 h. During annealing, an ultrathin PS-brush layer was formed making a covalent bond with hydroxyl groups on the surface of Al₂O₃. The unreacted portion of PS was removed by soaking in toluene solvent. Then the PS-brush treated substrates were again annealed for 24 h in a vacuum oven. Mechanically exfoliated MoS₂ and MoSe₂ flakes were transferred in sequence on a specific position of the PS-brush/Al₂O₃, where the patterned bottom gate was located. Finally, we deposited and patterned Au (70 nm) as the source and drain electrode by the same processes used for the gate electrode. Here, Au was chosen in consideration of its long-term stability although Ti contact would be better in charge injection as shown in Supplementary Fig. 8.

Device measurements

Basic electrical measurements of our devices were performed with a semiconductor parameter analyzer (Agilent 4155 C) in the dark at room temperature. The capacitances of dielectric materials were measured by a precision LCR meter (Agilent 4284 A) under the same conditions. For the multilevel long-term memory and the artificial synaptic device measurements, a pulse generator (81104 A, Keysight) was used to apply electrical pulses with various amplitudes, widths, and time intervals.

Materials characterization

Cross-sectional STEM samples were prepared by using a focused ion beam (FEI Helios 650 dual beam) for STEM and EDS measurements. Their STEM images and EDS mapping were obtained by transmission electron microscopes (JEOL ARM-200F equipped with image and probe aberration correctors) at 200 kV. Raman spectra were obtained with a 532-nm wavelength laser (LabRam Aramis, Horriba Jovin Yvon). A scanning probe microscopy (NX-10, Park system) was used for SKPM measurements.

Array simulation

“NeuroSim+” simulator was utilized for the ANN simulation. An MLP neural network was composed of 784 input neurons, 100 hidden neurons, and 10 output neurons. The input layer of 784 neurons corresponded to the postprocessing 28 × 28 pixels of an MNIST image. Ten neurons of the output layer matched with ten classes of digits from 0 to 9. For the simulation of recognition accuracy calculations, the SGD algorithm was applied for training based on the potentiation-depression plots of our stack channel FET characteristics.