Extended Data Fig. 9: Benchmarking and tomography of universal two-qubit logic.
From: High-fidelity spin qubit operation and algorithmic initialization above 1 K
a, An example random sequence with the microwave and voltage pulses generated by the FPGA. A DCZ gate includes two voltage pulses separated by an echoing two-tone X(π) pulse. The voltage pulse shape is designed to cancel any slow drift and compensation is applied to P1, P2 while exchange is being pulsed. We set a padding of 0.02 μs between two adjacent pulses. The real-time logic required for the FPGA to apply the sequences incur unintended gaps in the order of 0.1 μs between some of the quantum gates. This introduces both coherent and incoherent errors. Ensuing efforts should target the minimisation of real-time logic and accurate synthesis of waveforms prior to the sequence run. b, The experiment and analysis protocols for two-qubit randomised benchmarking and FBT. The experimental gate sequences consist of random Clifford gates Ci in the two-qubit space with a recovery gate R at the end. We then perform a projection P in +ZZ (no operation before parity readout) projection and -ZZ (π pulse on a single qubit before parity readout). c, IRB results at B0 = 0.79 T, T = 0.1 K and 1 K. d, Pauli transfer matrices (PTMs) for the DCZ gate at B0 = 0.79 T, T = 0.1 K and 1 K, determined by FBT. Error bars represent the 95 % confidence level.