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I've been looking through bits of documentation about the (sadly recently discontinued) Z80 processor and the machines people have built with it. One thing I noticed is pin 27, called "M1", which is used to indicate when the "Z80 is fetching next instruction from memory". I'm left wondering what the purpose of this pin is. I have done some work with other microprocessors and I've never seen a pin like it before.

I know machines like the ZX80 and ZX81 would stop the system clock when they needed up update the screen (something similar happens to the ZX Spectrum when reading the lower 16Kb of RAM). I could imagine that Sinclair might have made use of this pin so they know when they can stop the clock, but obviously that isn't why Zilog created the pin in the first place.

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    Question is different but several of the answers may be relevant to you: retrocomputing.stackexchange.com/q/4376/332
    – davidbak
    Commented Jun 24 at 18:20
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    It was useful fpr debugging (as well as other things described in the linked question). Z80 M1 signals might be interesting, w.r.t. the Spectrum.
    – Greenonline
    Commented Jun 24 at 18:43
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    Does this answer your question? Separate code and data address spaces on the Z80
    – Greenonline
    Commented Jun 24 at 18:44
  • ZX Spectrum does not use this signal and until you attach some peripherals to it like DivMMC you could never know that M1 is actually burned out. The latter might happen because of stupid connector pinout where M1 is situated next to +12v.
    – lvd
    Commented Jun 25 at 6:09

3 Answers 3

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Besides the literal purpose of knowing when an instruction is being fetched it was in practice used as a timing hint.

Most reads and writes on a Z80 take three cycles and whatever is on the other side of the data bus — ROM, RAM, whatever — has about two cycles in which to put something stable on the data bus after MREQ goes low.

Instruction fetches diverge from that pattern: only two cycles are used for reading an instruction, and peripherals get only around a cycle to respond to the relevant MREQ.

Many machines hold WAIT for a single cycle in response to M1, therefore getting a roughly-two-cycle length of time for all memory accesses.

The ColecoVision and MSX are examples of machines that do so.

With apologies for the stylistic differences owing to different sources furnishing the images, here are the standard read and write cycles:

Z80 read and write cycles

Note for reading that that MREQ goes low shortly after the midpoint of T1 (i.e. the first cycle) and the period marked 'In', when the processor samples the data bus, hangs over but mostly just barely before the midpoing of T3 (i.e. the third cycle).

Conversely, for an M1 cycle — with fair warning that everything has clearly been rounded to the half-cycle here, and some non-Z80 lines seem to have been added:

Z80 M1 cycle

MREQ goes low halfway through T1 much as before, but the period during which the CPU requires valid data to be on the data bus now begins halfway through T2, only one cycle later.

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As an addition to the other answers:

The Z80 used the combination of M1 and IORQ to signal interrupt acknowledge. Zilog calls this a "special M1 cycle."

BTW, just the CMOS CPU series by Zilog went out of production this April. Z80 lives on.

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    I guess that makes extra sense when you consider that the 8080-compatible interrupt mode expects you to place an instruction onto the bus to respond to an interrupt, conventionally an RST appropriate to the interrupting device.
    – Tommy
    Commented Jun 25 at 12:23
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One thing I noticed is pin 27, called "M1", which is used to indicate when the "Z80 is fetching next instruction from memory".

That's what it does.

I'm left wondering what the purpose of this pin is.

Exactly as described: telling when an opcode is fetched.

I have done some work with other microprocessors and I've never seen a pin like it before.

Might be interesting to learn what CPU's you have used so far (*1), but having a signal like that was quite common - heck, already Intel's 8008 signalled a PCI cycle.

Some examples:

Even systems with asynchronous bus operation offer similar signals, like Intel's 8086ff signalling fetch of the first byte of an instruction via its Queue Status (QS1,QS0 = 01). So to me this seems like a pretty common output for CPUs.

I know machines like the ZX80 and ZX81 would stop the system clock when they needed up update the screen.

No, they did not. The CPU was running during screen update, fetching screen data.

but obviously that isn't why Zilog created the pin in the first place.

What about

  • Hardware single step
  • Counting instructions
  • Inserting instructions
  • Stretching instruction fetch for slow memory
  • DMA insertion only at instruction borders
  • Bus arbitration in a multi master system

... and many more. Let your imagination flow - if your application has a corresponding real-time need, you'll know :))

*1 - Note, the Z80 is a CPU, not a microcontroller.

*2 - Which is where M1 got its name from, as bit D5 of the status word outputted during SYNC is called that.

*3 - At least the original ARM1 :))

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