Bob Grim’s Post

Increasing complexity in chip design results in more potential failure modes, and so engineers need to find new ways to ensure the quality and reliability of components. #reliabilityengineering #qualityassurance #failureanalysis https://lnkd.in/gqFp3qYb

Nice article on the changes underway in #semiconductors and the #geopolitics from Hannah Thoreson! https://lnkd.in/eRcsqZqU #opensource #hardware #riscv #chipflow

Here are the latest advancements in #automotive technology! See how the S32G3 family from NXP Semiconductors amplifies compute silicon for #safety, networking, and #security. Are you ready to learn more? Check out this article 👇

This week in our interview with Elie Rosen from BLT - Bottom Line Technologies we had a chance to ask an #fpga expert about the design trade offs of an FPGA vs an #asic Check out Elie's answer below: "The best case for going ASIC is for when you’re expecting to be producing, say, a couple hundred to over a thousand plus parts, especially if the design will require faster speeds that most FPGAs can support. Typically, it’s still a good practice to prototype as much as possible on an FPGA before taping out to reduce overall risks (ASIC manufacturing costs are expensive after all). Summary for ASIC Pros: Higher Speed More precise architecture (i.e., less overhead), lower power Faster boot time! A good counterexample to the ASIC route sometimes comes in the defense world. One of the benefits of using an FPGA is that your application may require multiple algorithms and many FPGAs offer a capability to partially reconfigure the device. In those cases, you could swap an algorithm on the fly and still use a smaller device to fit everything. Summary for FPGA Pros: Unlimited reconfiguration Specialized Hard IP which varies by device Likely lower cost and faster time to market" You can find the full interview with Elie at the link below, don't forget to subscribe to The Analog for more weekly content. https://lnkd.in/ea8w_jKM

Designing systems on a chip (SoC's) involves understanding how to optimize memory for improved performance and speed. #electricalengineering #chipdesign #memory https://lnkd.in/e87uUxqx

Founding of RISC-V Alliance Could Shake-Up Processor Sector A semiconductor technology alliance featuring industry heavyweights Qualcomm, Infineon Technologies, NXP Semiconductors, Robert Bosch and Nordic Semiconductor has just been established. Though details are still fairly limited, the participating companies involved have stated that they will focus on building a comprehensive ecosystem around the RISC-V architecture - serving the global engineering community through advanced hardware development. They will look to further the commercialisation of products based on this open-source architecture, providing solutions that share compatibility. Each will be making significant financial investments and allocating considerable amounts of engineering resource into this alliance, with the majority of the activity expected to be undertaken in Europe. Some have already interpreted this to be an attempt to unseat... READ MORE https://lnkd.in/drG6fJuy #riscv #microprocessors Ziad Asghar Svein-Egil Nielsen Jens Knut Fabrowsky Peter Schiefer Lars Reger

Curious 🤔 how Physical Design Engineers achieve peak efficiency in Power? Check out our newest blog on Power Optimization techniques in VLSI Physical Design: https://lnkd.in/g6rM8N7z Discover the secrets behind effortless innovation!

Transistor Basics And Their Role Today In this day and age of highly integrated chips, what is the relevance of the lone, discrete transistor? It’s true that most embedded system design needs can ...CLICK TO READ MORE https://lnkd.in/eqcMa9aJ #DCDCConverter

Great intro on cache coherency by my Arteris colleague Andy Nightingale. This goes together well with the additional details in the recent Semiconductor Engineering article here: https://bit.ly/48GadbO. "Designers can strategically balance the need for data consistency in specific areas while benefiting from more streamlined communication channels where strict coherence is unnecessary. In today’s sophisticated heterogeneous SoCs, the synergy between coherent and non-coherent interconnects becomes a strategic advantage, enhancing the overall efficiency and adaptability of the system." #Arteris #NetworkOnChip #SoCIntegrationAutomation #SystemOnChip #Semiconductor #ArtificialintelligenceAI #PhysicallyAwareNoC #CacheCoherency https://bit.ly/42eHskp

Here are the advances in #automotive technology! 🤩 NXP Semiconductors' S32G3 family provides a perfect example of enhanced compute silicon for #safety, networking, and #security. Read the full article to find out more!