Nigel Drego

Core-to-core variability in future many-core chip multi-processors (CMPs) negatively impacts energy. Under-performing cores necessitate increasing the system voltage to maintain homogeneous core performance, introducing an energy overhead. Multiple supply voltages can be used to mitigate the impact of delay variation in CMPs. In this paper, we carefully analyze the use of a local search algorithm to pick near-optimal supply voltages while meeting a fixed performance target. With two system… Show more

Core-to-core variability in future many-core chip multi-processors (CMPs) negatively impacts energy. Under-performing cores necessitate increasing the system voltage to maintain homogeneous core performance, introducing an energy overhead. Multiple supply voltages can be used to mitigate the impact of delay variation in CMPs. In this paper, we carefully analyze the use of a local search algorithm to pick near-optimal supply voltages while meeting a fixed performance target. With two system voltages, we prove our algorithm selects the global optimum and in the more general multiple voltage case we develop quantitative bounds. Using a custom simulation methodology on a real processor core, we show that two system voltages provide the most incremental benefit, reducing the energy overhead relative to a single voltage by 59-75% and total energy by 6-16%. Additionally, the worst 5-15% of cores in such systems necessitate increasingly larger amounts of incremental energy for a constant incremental performance gain. Therefore, turning off or disabling these cores is beneficial to a joint performance-energy metric. Show less

Increased variation in CMOS processes due to scaling results in greater reliance on accurate variation models in developing circuit methods to mitigate variation. This paper investigates spatial variation in digital circuit performance: we describe a test-chip in 90 nm CMOS containing all-digital measurement circuits capable of extracting accurate variation data. Specifically, we use replicated 64-bit Kogge-Stone adders, ring oscillators (ROs) of varying gate type and stage length and an… Show more

Increased variation in CMOS processes due to scaling results in greater reliance on accurate variation models in developing circuit methods to mitigate variation. This paper investigates spatial variation in digital circuit performance: we describe a test-chip in 90 nm CMOS containing all-digital measurement circuits capable of extracting accurate variation data. Specifically, we use replicated 64-bit Kogge-Stone adders, ring oscillators (ROs) of varying gate type and stage length and an all-digital, sub-picosecond resolution delay measurement circuit to provide this data. Measurement data from the test-chips indicate that 1) relative variation is significantly larger in low-voltage domains, 2) within-die variation is spatially uncorrelated, and 3) die-to-die (or global) variation is strongly correlated, but degrades toward uncorrelated as the power-supply voltage is lowered. Lastly, extended analysis of the data reveals that systematic effects such as layout pattern dependencies or circuit structure can be misinterpreted as random but spatially-correlated variation. This suggests that circuit designers will reap more benefit from design tools capable of modeling systematic, position-dependent variation rather than spatially correlated, distance-dependent variation. Show less

My PhD Thesis

Due to increased variation in modern process technology nodes, the spatial correlation of variation is a key issue for both modeling and design. We have created a large array test-structure to analyze the magnitude of spatial correlation of threshold voltage (VT) in a 180 nm CMOS process. The data from over 50 k measured devices per die indicates that there is no significant within-die spatial correlation in VT. Furthermore, the across-chip variation patterns between different die also do not… Show more

Due to increased variation in modern process technology nodes, the spatial correlation of variation is a key issue for both modeling and design. We have created a large array test-structure to analyze the magnitude of spatial correlation of threshold voltage (VT) in a 180 nm CMOS process. The data from over 50 k measured devices per die indicates that there is no significant within-die spatial correlation in VT. Furthermore, the across-chip variation patterns between different die also do not correlate. This indicates that Random Dopant Fluctuation (RDF) is the primary mechanism responsible for VT variation and that relatively simple Monte Carlo-type analysis can capture the effects of such variation. While high performance digital logic circuits, at high VDD, can be strongly affected by spatially correlated channel length variation, we note that subthreshold logic will be primarily affected by random uncorrelated VT variation. Show less

Increased variation in CMOS processes due to scaling results in greater reliance on accurate variation models in developing circuit methods to mitigate variation. This paper investigates specific variation parameters and their measurement approach for use in such models, leading to critical considerations in aggressive voltage scaling systems. We describe a test-chip in 90 nm CMOS containing all-digital measurement circuits capable of extracting accurate variation data. Specifically, we use… Show more

Increased variation in CMOS processes due to scaling results in greater reliance on accurate variation models in developing circuit methods to mitigate variation. This paper investigates specific variation parameters and their measurement approach for use in such models, leading to critical considerations in aggressive voltage scaling systems. We describe a test-chip in 90 nm CMOS containing all-digital measurement circuits capable of extracting accurate variation data. Specifically, we use replicated 64-bit Kogge-Stone adders, ring-oscillators (ROs) of varying gate type and stage length and an all-digital, sub-picosecond resolution delay measurement circuit to provide spatial variation data for digital circuits. Measurement data from the test-chips indicate that 1) relative variation is significantly larger in low-voltage domains, 2) within-die variation is spatially uncorrelated, and 3) die-to-die (or global) variation is strongly correlated, but degrades toward uncorrelated as the power-supply voltage is lowered. Show less

A test-structure comprising a dual-slope integrating analog-to-digital converter, auto-zeroing circuitry, digital control logic and a large array of devices under test (DUTs) has been developed to isolate threshold voltage variation. Threshold-voltage (VT) isolation is achieved by testing all DUTs in the subthreshold regime where drain-to-source current is an exponential function of VT. Spice simulations show that the structure is at least an order of magnitude more sensitive to VT variation… Show more

A test-structure comprising a dual-slope integrating analog-to-digital converter, auto-zeroing circuitry, digital control logic and a large array of devices under test (DUTs) has been developed to isolate threshold voltage variation. Threshold-voltage (VT) isolation is achieved by testing all DUTs in the subthreshold regime where drain-to-source current is an exponential function of VT. Spice simulations show that the structure is at least an order of magnitude more sensitive to VT variation than to channel length variation. This, in combination with a hierarchical access scheme and leakage control system, allows efficient characterization of DeltaVT for ~70,000 NMOS and ~70,000 PMOS devices in a dense 2mm x 2mm DUT array. Show less

My Master's Thesis

Data acquisition (DAQ) electronics are described for a system of high-rate cathode strip chambers (CSC) in the forward region of A Toroidal LHC ApparatuS (ATLAS) muon spectrometer. The system provides serial streams of control signals for switched capacitor array analog memories on the chambers and accepts a total of nearly 294 Gbit/s in serial raw data streams from 64 chambers in the design configuration. Processing of the data is done in two stages, leading to an output bandwidth of 2.56… Show more

Data acquisition (DAQ) electronics are described for a system of high-rate cathode strip chambers (CSC) in the forward region of A Toroidal LHC ApparatuS (ATLAS) muon spectrometer. The system provides serial streams of control signals for switched capacitor array analog memories on the chambers and accepts a total of nearly 294 Gbit/s in serial raw data streams from 64 chambers in the design configuration. Processing of the data is done in two stages, leading to an output bandwidth of 2.56 Gbit/s. The architecture of the system is described, as are some important signal processing algorithms and hardware implementation details. Although designed for a specific application, the architecture is sufficiently general to be used in other contexts. Show less