Lloyd Ramseyer

🎉 Greetings, fellow digital design aficionados! 🚀 Exciting strides ahead! Today marks Day 61 of our #100DaysRTL challenge, where we embark on another journey within the realm of Verilog. Our focus now shifts from the D flip-flop to the dynamic world of JK flip-flops. 🔁 🔍 Transitioning from D to JK: Unveiling the Evolution 🔍 Moving from a D flip-flop to a JK flip-flop involves an evolution in functionality, expanding possibilities while maintaining structural integrity. The JK flip-flop introduces additional versatility by incorporating both Set and Reset functionality within a single entity. 🌟 🔎 How Does it Function? 🔎 Conceptually, the JK flip-flop extends from the foundation of the D flip-flop, integrating distinct J (set) and K (reset) inputs. This advancement enhances flexibility by enabling both set and reset operations without the need for supplementary logic gates. 🤔💡 ⏱️ Balancing Complexity and Adaptability ⏱️ The JK flip-flop strikes a balance between complexity and adaptability, offering a comprehensive solution for sequential circuitry with its integrated set and reset capabilities. 🛠️🔍 Despite its augmented functionality, the JK flip-flop maintains versatility, serving as a pivotal element in various sequential circuits, registers, and counters. 🌟 🔧 Implementing in Verilog 🔧 Integrating a JK flip-flop in Verilog entails leveraging the foundational structure of a D flip-flop while accommodating the J and K inputs. This modification streamlines the design process and enhances clarity. 🧩 ✨ Feedback mechanisms are refined, typically achieved through conditional statements or logical operations to facilitate dynamic set and reset functionality. 🤖💻 🔮 In Conclusion 🔮 Within the dynamic tapestry of digital design, the JK flip-flop emerges as a versatile cornerstone, offering integrated set and reset capabilities alongside enhanced flexibility. 💡✨ Whether crafting registers, counters, or sequential logic circuits, the JK flip-flop assumes a pivotal role in ensuring synchronization and enabling seamless transitions between states. 🚀 As you delve deeper into the intricacies of digital circuitry, embrace the adaptability and robustness of the JK flip-flop, evolving your designs to new heights of efficiency and ✨ For more insights into RTL Designs, visit my GitHub Repo:https:https://lnkd.in/gRYMPpu6 Let's maintain the Verilog coding momentum throughout our hashtag #100DaysRTLchallenge! 💪 #Verilog #DigitalDesign #RTLDesign #verificationengineer

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Here's a little story for managers. ✍🏼 Let me know your thoughts ♻️ Repost if you enjoyed it 🧲 Join 2.4K+ others in my RF engineering newsletter (link in bio/comments)

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😔 Intel Instability Has You Down? Prime Day Has You Covered with AMD CPU Deals! 🎉 Scared by Intel's latest issues? Check out these amazing AMD CPU deals this Prime Day: 💥 AMD Ryzen 7 7900X💥 ✅ 12 cores, 24 threads, 5.6 GHz boost, 64 MB L3 cache ✅ Deal: $329.99 at Newegg (save $219) ✅ Why: Underrated powerhouse, great for gaming and multitasking. 🎮 AMD Ryzen 7 7900X3D 🎮 ✅ 12 cores, 24 threads, 5.6 GHz boost, 128 MB L3 cache ✅ Deal: $327.98 at Amazon (save $272) ✅ Why: Enhanced with 3D V-cache for top gaming performance. Upgrade your system with these top AMD CPUs and enjoy smooth, crash-free gaming! 💪🖥️ 👀 Read and see AMD Prime Day Deals here: https://flip.it/O.K.Ao #amd #gaming #intel #cpu

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In about 2 minutes, you'll get an idea of why formal? what we have done with it? and the scale of designs we have verified with formalISA. From bugs, to proofs, and intelligent debug and coverage we have spent 5 years testing this product in field. We can debate all we like, but it may be better to just do it! #formalverification #riscv #socformal

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Jim Keller, former Intel, AMD, and Tesla engineer, aims to challenge Nvidia's dominance in AI with Tenstorrent's energy-efficient chip design. Tenstorrent's upcoming second-generation AI chip promises superior energy and cost efficiency, presenting a viable alternative to Nvidia's offerings. The innovative design of Tenstorrent's chip features independent decision-making cores, potentially reshaping AI chip technology across diverse applications. #AI #Nvidia #semiconductor #semiconductors #chip #technology #innovation #research #computing Tenstorrent NVIDIA https://lnkd.in/g6a3vAu4

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You may find this interesting if you’re into #formalverification!

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#Needed #Quickly! #Semiconductor #Experts By— Surajeet Das Gupta | May 01, 2024 ||Semiconductor makers #need #thousands of #engineers and #technicians, and though #India 🇮🇳 has one of the largest pool of engineers in the #world, they do not have experience in the semiconductor #manufacturing space.|| The government, based on feedback from semiconductor companies operating in India, expects hundreds to thousand-odd Indian engineers to return from Southeast Asia and the United States to participate in the country's high-tech manufacturing revolution. "Nearly 20 to 25 per cent of the senior talent in the semiconductor manufacturing industry globally are Indians. We expect many of them to come back to India," says #Communications, #IT, and Railway #Minister #AshwiniVaishnaw. According to a top official in the #ministry of #electronics and #information #technology (#Meity), the #engineers who have decided to #return to #India from the #US are younger, while those from #Taiwan, #Singapore, and #Malaysia are generally over 45 years and with more experience. The official says that in the #US, the senior and therefore older semiconductor professionals whose families have settled down do not want to move out. But in Southeast Asia, many want to return home and are looking for opportunities. The response to the Tata group's recruitment drive in Taiwan for its OSAT (#outsourced #semiconductor #assembly and #test) and #fabrication (#fab) plant is a case in point, says the Meity official. #Tata #Electronics held roadshows in Taiwan's chip manufacturing centre of Hsinchu to attract professionals with 5 to 18 years of experience in yield, automation and equipment, among other fields. The company has tied up with Taiwanese chipmaker PSMC for technology, and its engineers may undergo training with the company. #AppliedMaterials #Applied #Materials #ATMP (#assembly, #testing, #marking, and #packing) #plant #OSAT #PSMC #technology #makeinindia India Semiconductor Mission Semiconductor Nation - Campus Connect #Details: ⤵️ https://lnkd.in/gyhRsfBk

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THE TWO SIDES OF SIGNAL INTEGRITY. Successful high-speed system design hinges on achieving integrity in the two signals below (blue and red). They are: (1) the input to your Rx after a lossy channel (blue), and (2) the output of your Rx Equalization (EQ, red) where bitstream logic levels are determined. Let’s talk about the biggest issues affecting both signals. (1) Blue Signal (Rx input). With loss in today’s channels approaching 40 dB, a 1 Volt launched at a Tx arrives at the Rx as only 10 mV. Because the slightest wiggle or change in slope is actually a bit change, this signal must arrive with 10 mV accuracy. Look closely at the (blue) signal and you’ll see what I mean. Small (10 mV) signal impairments due to impedance discontinuities in your PCBs, connectors, vias, etc. will raise your Bit Error Rate (BER). This is the #2 cause of serial link failure, and the focus of my 5 posts last week. (2) Red Signal (Rx EQ output). For more than three generations of serial links, signal integrity/performance has been measured beyond the Rx EQ deep inside the IC (red). As the image (below) reveals, this is the only place an eye opening – and hence valid logic levels – is visible (compare blue and red eyes). Incorrect/non-optimal Tx/Rx EQ settings is the #1 cause of link failures, so correcting EQ will be the topic of this week’s posts. Many times Tx EQ needs to be turned off or used only for pre-cursors, thus preserving signal amplitude. Not sure what that means? Stay tuned. Blue and Red - these define the two days in my LIVE Masterclass. On Day 1 (blue) we discuss the ‘new school’ SI skills you need to deliver signals through your passive interconnect with 10 mV accuracy. On Day 2 (red) attendees learn how to read EQ’d pulse responses to open eyes and improve BERs ‘hands-on’ using labs that show quintillions of bits with the click of a mouse. Don’t miss out. June 5/6 SI Masterclass in Silicon Valley: https://lnkd.in/dY7KiKmX #signalintegrity #siforees

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NY senator breaks a spoiler to AP: Micron Technology to receive $6.1B from the Chips Act. Excerpts from Boise (Idaho) Development : "Micron Technology will get $6.1 billion from the CHIPS Act to fund large-scale expansions in Boise and Syracuse, NY. ... Micron has started work on a $15-billion expansion of its Boise campus, which would add significant new research and development capacity to the site off Federal Way. The City of Boise annexed nearly a square mile of new land for Micron, and work has begun on initial infrastructure. The Boise expansion would add nearly 2,000 local jobs, the company said. ... In addition to the federal funds, Micron will get incentives from the State of Idaho as well as some non-direct assistance from the City of Boise, as BoiseDev previously reported. ... Micron will also build a nearly $100-million facility near Syracuse, New York, which Schumer said to the AP is the largest single investment in that state since the Erie Canal. ... Schumer told Syracuse.com that the deal was preliminary and non-binding and could be announced next week. ... Correction: A prior version of this story incorrectly stated that the reported mount was $5.1 billion. It is $6.1 billion." https://lnkd.in/gCByqhnb

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Before I worked in the #semiconductorindustry, I worked as a civil engineer. I found this article about CalTrans using #AI to answer complex traffic-related questions fascinating. "Caltrans says the data generated from traffic sensors and cameras — coupled with the continuous velocity of data generation and the variety of videos, images, log files, third-party data streams and guidance — poses challenges for humans to digest and utilize." Sounds a bit like using #AI and #ML for smarter #scheduling in a #waferfab, doesn't it? More #industrialengineering than civil engineering.

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If you haven't heard of the graphics chip startup X-Silicon Inc yet, don’t worry… you'll soon be hearing their name everywhere. The company recently emerged from stealth mode amid a flood of exciting announcements that ranged from their novel graphics processing architecture to their platform that is being requested by premier RISC-V ecosystem partners. I had the pleasure of talking with X-Silicon’s CEO Dan Nilsson and Chief Scientist Atif Zafar a couple of weeks ago as they traveled to raise capital. After hearing from them, these two experienced technology leaders rightfully have reason to be excited about what they're building and will soon be bringing to market. The viewpoint we share is that graphics processing holds incredible potential to bring high-performance AI to the masses, however, graphics architectures are largely stuck in the 90s because they were developed in an era when PCs and smartphones were first gaining adoption but have received little attention and innovation since. X-Silicon promises a paradigm shift to upend traditional polygonal rendering and transition the industry to unrivaled performance. They plan to accomplish this through a software-first approach and will provide hardware and a graphics IP platform built from the ground up. This will usher in what they call the "Personal Cognitive and Edge AI Device Age." Hearing them describe this future—where low-cost, high-compute, AI-enabled devices are in the hands of billions around the world—was indeed exciting, and even though there are companies currently working on certain aspects of this vision, X-Silicon believes they have a holistic understanding of the problems and opportunities and has solutions to address them all. Hear why Dan and Atif believe their “time is now” in the video segment below and keep an eye on this team in the weeks and quarter ahead as we approach the RISC-V Summit in October. I’m confident they will have more news very soon! #riscv #GPU #artificialintelligence

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Non-Inverting Summing Amplifier and Precision Differential Amplifier: From my study note.

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I have been saying this for years and years: The RISC-V ISA is an open specification, not open source! Terminology is important, so quit being lazy and stop calling ANYTHING with the RISC-V label open source without being specific. Your RISC-V CPU implementation might be a closed, proprietary implementation of an open standard ISA. The Register gets it right-- Bravo! #riscv #cpu #unitedstates #senate https://lnkd.in/gd2rz8dM

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Check out my new blog on using our #radhard #MCU to reconfigure #Space deployed #FPGA. Please reach out if you have interest and we can provide specific details on how to deploy

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In the fiercely competitive semiconductor industry, companies are in a constant battle to retain top talent because in the heart of every good engineer is a passionate problem solver, looking for their next challenge. For them, innovation is the currency of success. Yet companies like Qualcomm, Intel, and Broadcom attract tens of thousands every year by dangling lucrative compensation packages to lure them from competitors. Startup leaders don’t have those resources, so they have to work harder to attract the best talent and then fight like hell to retain them. But some of the most successful startup leaders I know take a different approach. Rather than viewing attraction and retention as a fight, they leverage the inherent qualities of their companies as their advantage. They use their nimbleness, bias toward innovation, and their collaborative cultures like superpowers to attract the right people and those usually end up being the reasons why people stay. Take Richard Fung, CEO of The Six Semiconductor, for example. I had a conversation with Richard and asked him to share his approach to motivating his team. His response was like a mini-masterclass on the topic of talent attraction and retention. Richard emphasized that a culture that encourages engineers to dive deep into the intricacies of their craft, understand the systems they’re building, and connect with the end customer is a successful culture. Richard has been using this approach and it's been paying dividends for The Six Semiconductor so in his honor, here are his six key concepts for creating this type of organization: 1. Foster a Learning Culture: Support ongoing learning and skill development beyond employees' core responsibilities. 2. Prioritize Customer Focus: Embed a customer-centric mindset, and encourage employees to enhance user experiences through their work. 3. Champion Problem-Solving: Empower employees to creatively solve challenges with a focus on customer needs. 4. Promote System-Level Understanding: Encourage employees to grasp the bigger picture of the company's offerings and their role within it. 5. Break Down Silos: Promote collaboration to ensure a comprehensive understanding of projects across teams. 6. Offer Meaningful Challenges: Provide intellectually stimulating projects that make a tangible impact on the company's success. What Richard highlighted is that success goes much deeper than getting great people to join. It's about unleashing the full potential of every individual on your team to drive innovation and help shape the company, and ensuring your team heads in the right direction together. I’m thrilled I got to learn Richard’s perspective and believe other leaders can benefit from hearing it, so I shared the video below. My "challenge question" to other startup leaders is this: what are you doing to foster this type of culture in your organization? Either share below or, feel free to DM me. #semiconductorindustry #startup #leadership

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Output impedance of a Wilson Current Mirror The Wilson current mirror was quite popular in the BJT era, but is now obsolete in the CMOS era, probably due to the relatively high voltage requirements. Nonetheless, computing its output impedance can be insightful in several ways. In the following video, I discuss about: - Identifying the kind of feedback in a system and how it helps our cause - Recognizing the blocks that we are already familiar with so that we can utilise our previous learnings to make our life as circuit designers easier. - Computing the output impedance of the Wilson Mirror - The worst case corner of a circuit (poll conducted previously) Link: https://lnkd.in/gt3Pw7g6 Follow Tejas Ketkar to stay updated with such content. #circuits #interview #vlsi #semiconductors #analog

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Cadence Pegasus Verification System Have you ever wanted to write a DRC rule deck to check for space or width constraints on polygons? Or have you wondered how the multiple lines of an LVS rule deck extract and conduct a comparison between the schematic and layout? Read this blog to learn more. #Pegasus #Cadence #PhysicalVerification #DigitalDesign #Signoff https://ow.ly/9vCi50SxsS6

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🆕 AMD 5th-Gen EPYC™ "Turin" Announced at Computex 2024! 🌐 🔥 Why AMD Over Intel? ✅ Unmatched Performance: Up to 192 cores and 384 threads. AMD 5th-Gen EPYC™ "Turin" is 5.4X faster in AI workloads than Intel Xeon. ✅ Innovative Design: "Zen 5c" cores optimize space and power, enhancing core density critical for hyperscale environments. ✅ Easy Upgrades: Continues with SP5 socket compatibility, ensuring seamless transitions and faster server deployments. ✅ Growing Market Presence: AMD now commands 33% of the data center market, reflecting increasing trust in their technology. 👉 Stay Updated: AMD Meet the Experts webinar for a deeper dive into AMD 5th-Gen EPYC™ "Turin" coming soon! #AMD #EPYCTurin #DataCenter #AI #AMDvsIntel #TechTrends #DataCenterInnovation #EPYC

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