Information for "Transport triggered architecture"
Basic information
| Display title | Transport triggered architecture |
| Default sort key | Transport Triggered Architecture |
| Page length (in bytes) | 17,929 |
| Namespace ID | 0 |
| Page ID | 2830935 |
| Page content language | en - English |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of page watchers | 36 |
| Number of page watchers who visited in the last 30 days | 6 |
| Number of redirects to this page | 1 |
| Counted as a content page | Yes |
| Wikidata item ID | Q2329233 |
| Local description | Type of computer processor design |
| Central description | type of computer processor design |
| Page views in the past 30 days |
Page protection
| Edit | Allow all users (no expiry set) |
| Move | Allow all users (no expiry set) |
Edit history
| Page creator | PekkaJ (talk | contribs) |
| Date of page creation | 09:53, 4 October 2005 |
| Latest editor | R. Henrik Nilsson (talk | contribs) |
| Date of latest edit | 13:58, 15 December 2022 |
| Total number of edits | 123 |
| Recent number of edits (within past 30 days) | 0 |
| Recent number of distinct authors | 0 |