Information for "Back-side bus"
Basic information
| Display title | Back-side bus |
| Default sort key | Back-side bus |
| Page length (in bytes) | 4,130 |
| Namespace ID | 0 |
| Page ID | 339045 |
| Page content language | en - English |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of page watchers | Fewer than 30 watchers |
| Number of redirects to this page | 2 |
| Counted as a content page | Yes |
| Wikidata item ID | Q742323 |
| Local description | Computer architecture terminology |
| Central description | computer bus used on early Intel platforms to connect the CPU to CPU cache memory, usually off-die L2 |
| Page image |  |
| Page views in the past 30 days |
Page protection
| Edit | Allow all users (no expiry set) |
| Move | Allow all users (no expiry set) |
Edit history
| Page creator | 206.116.182.34 (talk) |
| Date of page creation | 00:01, 12 October 2003 |
| Latest editor | GhostCarrot (talk | contribs) |
| Date of latest edit | 15:33, 3 December 2023 |
| Total number of edits | 87 |
| Recent number of edits (within past 30 days) | 0 |
| Recent number of distinct authors | 0 |